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Inspire Semiconductor, Inc.

SoC Design Verification Engineer

Inspire Semiconductor, Inc.

📍 Austin, United States 🇺🇸

full-time
senior
hybrid
Posted —
Key Skills
SystemVerilog UVM RISC-V Python Git
Industry
Semiconductor Consumer Electronics

Job Description

About Us:


At InspireSemi, we're not just building a chip; we're revolutionizing high-performance computing. Our groundbreaking architecture packs thousands of 64-bit CPU cores onto a single chip, all tightly integrated with a high-performance interconnect. We're driven by a mission to make high-performance computing more accessible and energy-efficient, with a developer-friendly programming model. Ready to make a real impact? Join our passionate team!


Why Join InspireSemi?


  • Make an Impact: Your work will directly contribute to building a high-performance compute accelerator for scientific, AI, and other applications.
  • Rewarding Compensation: We offer competitive salaries, benefits, and equity.
  • Flexibility: Benefit from a hybrid work environment in our Austin office, with exceptional candidates considered for fully remote work.
  • Grow With Us: Contribute to the development and improvement of verification methodologies, tools, and automation scripts.


The Opportunity:


We are looking for a SoC Design Verification Engineer to support the complete verification of our innovative System-on-Chip (SoC). This critical role encompasses our RISC-V core, network, and 3rd-party peripheral IP integrations. You will be responsible for developing comprehensive verification plans, building testbenches, and ensuring the highest level of design quality and functional correctness before tape-out.


What You'll Do:


  • Develop and execute verification plans for complex SoC digital designs.
  • Create and maintain UVM/SystemVerilog based testbenches and environments.
  • Write, debug, and execute constrained-random and directed test cases.
  • Implement RISC-V ISA compliance tests.
  • Perform functional coverage analysis and close coverage gaps.
  • Perform regression runs, analyze failures, and drive bug closure.
  • Connect simulations to real user interfaces, stimulus generators, and checkers.
  • Collaborate closely with RTL design engineers, architects, and software teams.
  • Contribute to the development and improvement of verification methodologies and automation scripts.
  • Perform preliminary debug of discovered issues.


What You Bring:


  • A Bachelor's or Master's degree in Electrical, Electronics, or Computer Engineering (or related field).
  • 5+ years of hands-on experience in ASIC/SoC design verification.
  • Strong proficiency in SystemVerilog, UVM, and simulation tools (e.g., Xcelium).
  • Solid understanding of digital design fundamentals, RTL design, and synthesis flow.
  • Experience with functional coverage, assertions, and scoreboarding.
  • Strong scripting and programming skills (Python, Perl, TCL, C/C++).
  • Knowledge of common bus protocols (AXI, AHB, PCIe, DDR4/5, etc.).
  • Working knowledge of version control and continuous integration tools (e.g., Git, Jenkins, Jira, and Confluence).
  • Solid debugging skills, analytical thinking, and attention to detail.


Bonus Points:


  • Experience with Formal verification (Conformal LEC).
  • Hands-on experience with emulation systems (Zebu, Palladium) or FPGA prototypes.
  • Experience with Cadence EDA tools.


If you're excited about pushing the boundaries of computing and working on truly innovative technology in a rewarding environment, we'd love to hear from you!