Saransh

Design Verification Engineer - Remote

📍 United States, United States 🇺🇸

contract

mid-level

remote

Posted —

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SystemVerilogUVMsimulationtestbenchcoverage

SemiconductorAerospace

Role: Design Verification Engineer

Remote (must be aligned with PST time zone)

Job Type: Contract

Job Description

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs.
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

Qualifications

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in ASIC/SoC verification.
Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git).

Responsibilities

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.