Responsible for functional verification of CPU design, including the creation and maintenance of the verification environment.
Develop and implement constraint-random verification strategies to ensure the correctness and performance of the CPU and associated peripheral designs.
Utilize coverage-driven approaches for low-power verification to ensure stability and efficiency of the design across various power modes.
Implement formal verification and assertion-based verification to enhance the reliability of the design and reduce the error rate.
Analyze and address issues encountered during the verification process, working closely with the design team for problem diagnosis and correction.
Write and maintain technical documentation, including verification plans, test cases, and verification reports.
Keep up-to-date with the latest verification technologies and tools to continuously optimize verification processes and methodologies.
Requirement
Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
Experience in CPU or related digital circuit design verification.
Proficiency in HDL languages (such as Verilog or VHDL) and verification languages (such as SystemVerilog, UVM).
Familiarity with constraint-random verification methods and tools, such as solutions from Cadence, Synopsys, or Mentor Graphics.
In-depth knowledge of low-power design and verification techniques.
Practical experience with formal verification and assertion-based verification.
Strong problem-solving skills and a team player mentality.
Good communication skills in English and the ability to write technical documentation.