Assistant Manager – FPGA Engineering

This role is intended for professionals with 6+ years of relevant experience. Candidates who meet this requirement are encouraged to apply.

Assistant Manager – FPGA Engineering

Location: DHA Phase-II, Islamabad

Company: TeReSol Pvt. Ltd.

Experience Required: 6+ Years

Employment Type: Full-Time

About TeReSol

TeReSol Pvt. Ltd. is an innovation-driven engineering company specializing in embedded systems, FPGA development, and advanced hardware solutions. We are seeking a seasoned FPGA professional to join us as Assistant Manager – FPGA Engineering, responsible for leading complex design projects and mentoring a high-performing engineering team.

Role Overview

This role is ideal for an experienced FPGA engineer with strong technical leadership skills and hands-on expertise in FPGA development on AMD Zynq platforms. The selected candidate will lead end-to-end FPGA design activities, drive project execution, ensure technical excellence, and contribute to delivering high-performance hardware systems.

Key Responsibilities

• Lead and review RTL design (VHDL, Verilog, SystemVerilog) for AMD Zynq-based systems.

• Develop and maintain simulation testbenches for functional verification and coverage.

• Analyze timing closure issues, resolve bottlenecks, and optimize performance and resource utilization.

• Manage migration of RTL designs across FPGA generations and device families.

• Prepare architecture documents, simulation reports, and technical documentation.

• Collaborate with software, hardware, and system engineering teams.

• Conduct technical design reviews and approve design sign-offs.

• Mentor junior engineers and enforce coding and verification standards.

• Define verification methodologies, coding guidelines, and documentation practices.

• Manage project timelines, risks, and provide progress updates to senior management.

• Translate product requirements into clear engineering deliverables.

Technical Requirements

• Hands-on experience with AMD Zynq-7000 and/or Zynq UltraScale+ SoC/MPSoC platforms.

• Strong expertise in RTL design, timing closure, and digital design methodologies.

• Experience with AXI4 / AXI4-Lite / AXI4-Stream and PS–PL interfacing.

• Proficient in Vivado, Vitis, and PetaLinux environments.

• Experience in constrained-random and coverage-driven verification.

• Familiarity with FPGA resource and power optimization techniques and formal verification tools.

• Strong understanding of FPGA project structuring, IP integration, and version control (Git).

• Experience with Jira and engineering design review workflows.

Education

• Bachelor’s degree (B.Sc./B.E.) in Electrical, Electronic, or Computer Engineering (Required).

• Master’s degree or equivalent qualification (Preferred).

Apply Now

If you are passionate about FPGA innovation and technical leadership, we invite you to join TeReSol and be part of our growing engineering team.

Email: Apply at: [email protected]