Analog Layout Design Engineer

Experience: 3+ Years

Location: Hyderabad

Department: VLSI / Semiconductor Design

We are seeking a skilled Analog Layout Design Engineer with 3+ years of hands-on experience in custom layout design, including standard cell development. The ideal candidate will have strong expertise in Cadence Virtuoso and a solid understanding of analog and mixed-signal layout techniques.

• Design and develop high-quality analog and mixed-signal layouts (e.g., amplifiers, current mirrors, bandgaps, etc.).
• Perform standard cell layout design and optimization for performance, area, and power.
• Execute full custom layout from schematic to GDSII.
• Ensure layout complies with DRC, LVS, ERC and other physical verification checks.
• Work closely with circuit designers to understand design requirements and constraints.
• Apply layout techniques such as matching, shielding, guard rings, and common centroid.
• Perform parasitic extraction and support post-layout simulations.
• Optimize layouts for yield, reliability, and manufacturability .
• Collaborate with cross-functional teams including design, verification, and process engineers.

• 3+ years of experience in analog/custom layout design .
• Strong hands-on experience with Cadence Virtuoso (Layout XL, Virtuoso tools).
• Experience in standard cell layout design .
• Good understanding of:
• CMOS technology
• Analog layout best practices
• Device matching and symmetry techniques
• Familiarity with DRC/LVS tools (e.g., Assura, Calibre).
• Knowledge of parasitic extraction and post-layout simulation.
• Ability to read and interpret circuit schematics.
• Good problem-solving and debugging skills.

• Experience with advanced nodes (e.g., 28nm, 16nm, or below).
• Exposure to mixed-signal or RF layout .
• Knowledge of scripting (Skill, Python) is a plus.
• Understanding of reliability issues (EM, IR drop, ESD).