ASIC Physical Design Engineer

Company Description Verex Engineering LLC is a multi-cloud solutions, engineering, and healthcare technology company focused on helping organizations grow, increase efficiency, and innovate securely. The team designs and manages applications and infrastructure across leading cloud platforms, including AWS, Azure, and Google Cloud, in an integrated and cohesive way. By solving more than just technical workload challenges, Verex aims to create tangible business advantages and enable clients to work faster and smarter. Its multi-cloud engineering services span the full project lifecycle—from discovery and assessment through deployment, migration, optimization, and ongoing support—guided by industry best practices. The company leverages advanced tools and security frameworks to deliver reliable, compliant, and scalable solutions.
Role Description The ASIC Physical Design Engineer will be responsible for driving the implementation of complex digital ASICs from RTL handoff through tape-out, ensuring performance, power, and area targets are met. In this full-time, on-site role based in San Jose, CA, the engineer will perform floorplanning, place-and-route, clock tree synthesis, timing closure, and physical verification using industry-standard EDA tools. Day-to-day tasks include collaborating closely with RTL, logic design, verification, and architecture teams to define design constraints, analyze timing, and resolve functional and physical issues. The engineer will generate and maintain design collateral such as SDC constraints, methodology scripts, and sign-off reports, and support DFT, power intent, and ECO implementation. The role also involves participating in design reviews, improving physical design flows, and contributing to best practices for scalable, reusable physical design methodologies.
Qualifications

• Strong digital design foundation, including Logic Design and RTL Design for complex ASICs or SoCs.
• Hands-on experience in Physical Design, including floorplanning, placement, routing, clock tree synthesis, and timing closure.
• Proficiency in RTL Coding (e.g., Verilog/SystemVerilog or VHDL) and familiarity with design-for-test and low-power design techniques.
• Experience with Formal Verification and other verification methodologies to ensure functional correctness and sign-off quality.
• Proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence, or Siemens flows) for synthesis, STA, and physical verification.
• Strong understanding of timing concepts, signal integrity, power analysis, and physical verification (DRC/LVS).
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
• Ability to work collaboratively in cross-functional engineering teams, communicate clearly, and manage priorities in a fast-paced environment.
• Experience with advanced technology nodes and multi-clock or multi-voltage designs is a