ASIC Physical Design Engineer

Job Title: ASIC Physical Design Engineer

Location: Hyderabad

Experience: 4 8 Years

Job Type: Contract

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Working on enterprise-scale projects with global clients.

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Job Summary

We are looking for a highly skilled ASIC Physical Design Engineer with hands-on experience in advanced-node physical design implementation and signoff activities. The ideal candidate will have strong expertise in floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and tapeout activities for complex SoC/ASIC designs.

The selected candidate will work on cutting-edge processors, controller architectures, and ASICs within the Enterprise SSD domain, contributing to high-performance and low-power semiconductor products.

Key Responsibilities

• Perform block-level low-power-aware physical design implementation.
• Handle floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
• Execute RC extraction and Static Timing Analysis (STA) closure at block level.
• Perform IR Drop, Electromigration (EM), and power integrity analysis and closure.
• Drive physical verification closure, including DRC, LVS, Antenna, and ERC checks.
• Work on tapeout activities and signoff requirements.
• Analyze and optimize Power, Performance, and Area (PPA) metrics.
• Collaborate closely with design, STA, methodology, and signoff teams.
• Debug implementation challenges and provide innovative solutions to achieve design closure.
  
  

Mandatory Skills

• 4 8 years of hands-on experience in ASIC Physical Design implementation.
• Strong expertise in APR (Automatic Place & Route) flow development and PPA optimization.
• Experience in block-level STA timing closure.
• Hands-on experience with advanced technology nodes (5nm/3nm TSMC technologies).
• Strong working experience with Cadence tools:
• Innovus
• Tempus
• Experience in Physical Verification closure using Calibre:
• DRC
• LVS
• Antenna Checks
• Experience in IR Drop and EM analysis and closure.
• Knowledge of tapeout and signoff methodologies.
• Strong understanding of digital electronics and microprocessor architecture.

Skill Experience Required Innovus 4 8 Years Tempus 4 8 Years Calibre (DRC/LVS/Antenna) 4 8 Years Physical Design Implementation 4 8 Years STA Closure 4 8 Years TSMC 5nm/3nm Technologies Mandatory Mandatory Requirement

• Candidate must have hands-on experience working on TSMC 5nm and/or 3nm technology nodes.
• TSMC certification is highly preferred.
  
  

Preferred Skills

• Strong experience with Cadence PnR tool suite.
• Exposure to Formal Verification methodologies.
• Knowledge of digital electronics and microprocessor design.
• Experience working on high-performance SoC or ASIC projects.
• Strong understanding of physical signoff methodologies.
• Bachelor's or Master's Degree in Electronics Engineering, Electrical Engineering, Computer Engineering, VLSI, or a related field.