Key Skills
RTLLintCDCSoCSynthesis
Industry
SemiconductorConsumer Electronics
Job Description
Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications.
$114,000/year to $172,000/year + bonus + equity + benefits
Responsibilities
- Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC
- Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC
- Perform RTL Lint and work with the Designers to create waivers
- Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
- Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
- Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,)
- Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback
Minimum Qualifications
- Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 2 years of experience in static verification tools
- Experience with Lint, Clock Domain & Reset Domain crossing
- Experience with SOC CDC signoff
- Knowledge of SOC Integration (Clocking, Reset, PLL, etc)
- Knowledge of front-end ASIC flows
- Experience with RTL design using SystemVerilog or other HDL
- Experience with communicating across functional internal teams and vendors
Preferred Qualifications
- Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools
- Scripting and programming experience using Perl/Python, TCL, and Make
- Experience with Netlist-CDC Analysis and improving MTBF
- Experience with developing structural rule based checks for RTL & Netlist
- Knowledge of Timing/physical libraries, SRAM Memories
- Experience with SOC Design Integration and Front-End Implementation
$114,000/year to $172,000/year + bonus + equity + benefits
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Key Skills
RTLLintCDCSoCSynthesis
Industry
SemiconductorConsumer Electronics