ASIC Design Verification Engineer | SystemVerilog/UVM | Remote

We are actively seeking a Design Verification Engineer to join a cutting-edge wireless silicon development team. This is an exciting opportunity to work on custom ASIC/SoC designs and contribute to the development of next-generation silicon products.

Key Responsibilities:

✔ Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

✔ Build SystemVerilog/UVM testbenches including agents, monitors, scoreboards, checkers, and coverage models.

✔ Write SystemVerilog Assertions (SVA) and support formal verification activities.

✔ Drive constrained-random and directed testing strategies.

✔ Debug simulation failures, perform root-cause analysis, and collaborate with RTL design teams.

✔ Implement and maintain functional, code, and assertion coverage for sign-off.

✔ Manage regression testing, simulation environments, and CI pipelines.

✔ Participate in design reviews and microarchitecture discussions.

Required Qualifications:

✔ BS/MS in Electrical Engineering, Computer Engineering, or related field.

✔ 3+ years of ASIC/SoC Design Verification experience.

✔ Strong expertise in SystemVerilog and hardware verification methodologies.

✔ Experience with UVM-based verification environments.

✔ Hands-on experience with VCS, Xcelium, or Questa.

✔ Experience using Verdi, SimVision, or similar debug tools.

✔ Knowledge of constrained-random verification and coverage-driven methodologies.

✔ Familiarity with Python, Perl, or TCL scripting.

✔ Experience with Git or similar version control systems.