ASIC Design Engineer

Company Description Parade Technologies, Inc. develops and supplies integrated circuits for touch, display, and high-speed digital interface applications used in a wide range of consumer and commercial devices. The company serves a world-class global customer base, partnering with leading technology brands on next-generation products. Parade is recognized as an industry leader in mixed-signal circuit innovation and design, delivering advanced, cost-effective solutions that meet demanding performance and power requirements. Team members work in a fast-paced, technically rigorous environment with opportunities to contribute to high-impact silicon products. The company values collaboration, innovation, and high-quality engineering practices.

Role Description This full-time, on-site ASIC Design Engineer role is based in Beaverton, OR. The ASIC Design Engineer will be responsible for RTL design and coding of digital blocks and subsystems, including writing synthesizable RTL, developing micro-architectures, and integrating IPs into larger SoC or ASIC designs. Day-to-day work includes creating and reviewing logic design specifications, performing logic synthesis preparation, collaborating with physical design teams on timing, floorplanning, and design closure, and supporting design-for-test requirements. The engineer will also develop verification plans, work with verification teams on simulation and formal verification, analyze and resolve functional and timing issues, and contribute to design documentation and design reviews. Close collaboration with cross-functional teams such as architecture, analog/mixed-signal, validation, and product engineering is expected throughout the silicon development cycle.

Qualifications

• Must have at least 2 years of post-college industry experience.
• Strong digital design foundation, including Logic Design and RTL Design for complex ASIC or SoC blocks.
• Proficiency in RTL Coding using hardware description languages (e.g., Verilog, SystemVerilog or VHDL) and experience implementing micro-architectures from specifications.
• Experience with Physical Design interaction, including understanding of timing constraints, synthesis, place-and-route considerations, and design closure support.
• Hands-on Formal Verification experience, along with familiarity with simulation-based verification flows and debug.
• Proficiency with industry-standard EDA tools for design, verification, and synthesis (e.g., Synopsys, Cadence, Mentor/Siemens tools).
• Solid understanding of digital design concepts such as clocking, reset strategies, CDC, power optimization, and design-for-test principles.
• Strong problem-solving, debug, and analytical skills with the ability to own issues from discovery through resolution.
• Effective written and verbal communication skills and the ability to work collaboratively in cross-functional engineering teams.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Experience with high-speed digital interfaces such as PCIe, USB, or Display Port