Black Sesame
ASIC Design Engineer
Black Sesame
📍 Singapore, Singapore 🇸🇬
full-time
entry-level
Posted —
Key Skills
VerilogSystemVerilogC++ASICPython
Industry
SemiconductorAerospace
Job Description
Responsibilities
Additional Notes: Strong analytical skills and a willingness to learn and adapt in a dynamic environment.
- Assist in designing micro-architecture for ISP and CV algorithms.
- Perform RTL design using Verilog/System Verilog and HLS tools (Catapult).
- Support the analysis of metrics related to power, performance, and area.
- Collaborate with architects and DV Engineers to ensure efficient verification signoff.
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Help with FPGA tasks, including emulation, validation, and debugging.
- Education: Minimum Master’s degree and above in Electrical/Electronics/Computer Engineering.
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Experience: Entry-level position; relevant coursework or project experience in ASIC design or image signal processing is a plus.
- Experience/knowledge in Verilog/SystemVerilog and C/C++.
- Familiarity with ASIC design processes and frontend design.
- Knowledge of image/vision/video data processing or algorithm acceleration is beneficial.
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Familiarity with scripting languages (Python, Perl, Tcl) is a plus.
Additional Notes: Strong analytical skills and a willingness to learn and adapt in a dynamic environment.
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Key Skills
VerilogSystemVerilogC++ASICPython
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SemiconductorAerospace