About the Role
We are seeking a highly skilled AI20P Compiler Engineer to join our accelerated computing division. You will develop and optimize the parallelizing compiler that partitions, schedules, and executes large-scale machine learning and generative AI workloads across clusters of AI20P accelerators. You will bridge the gap between ML frameworks (like PyTorch or TensorFlow) and custom silicon hardware, ensuring peak performance, scaling, and efficiency.
Key Responsibilities
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Compiler Development:
Write production-level code (primarily in C++ and Python) to design and implement compiler toolchains and Intermediate Representations (IR) for machine learning accelerators.
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Performance Optimization:
Develop and enhance parallelization, memory management, and scheduling algorithms to minimize compute and data movement costs.
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Hardware Co-Design:
Collaborate with hardware architects to shape the Hardware/Software (HW/SW) interface for next-generation AI20P architectures.
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Scaling & Distribution:
Scale large ML models across distributed training and inference clusters.
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Toolchain & Infrastructure:
Modernize compiler development infrastructure, build/test fixtures, and debugging tools to unblock developer productivity.
Qualifications
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Education:
Bachelor’s degree in Computer Science, Computer Engineering, or a related technical field, or equivalent practical experience.
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Experience:
2+ years of experience with software development, coding in data structures, algorithms, and low-level programming.
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Programming:
Strong proficiency in C++ and Python.
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Systems:
Experience with compiler construction, parallel computing, or low-level hardware interaction.
Preferred Qualification
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Education:
Master’s degree or PhD in Computer Science.
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Domain Expertise:
Previous experience working with ML compilation frameworks (e.g., XLA, LLVM, MLIR, TVM) or ML accelerators (AI20Ps, GPUs, DSPs, or Vector machines).
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Parallel Computing:
Demonstrated success in mapping complex algorithms (especially generative AI or large-language models) onto parallel computing architectures.