Sr Staff Engineer, Compiler

As an AI Compiler Engineer on the Renesas HPC team, you will be responsible for driving compiler and code generation technologies that unlock the full compute potential of Renesas next-generation automotive System-on-Chip platforms, including advanced 3 nm silicon for software-defined vehicles (SDVs). Your work will directly impact how AI workloads Рђћ from perception and sensor fusion to in-vehicle assistants and advanced driver assistance Рђћ are translated into highly optimized, safe, and power-efficient execution on Renesas hardware.

This role bridges software compiler development, AI model lowering/optimization, and hardware-software co-design, enabling Renesas SoCs to deliver industry-competitive performance, efficiency, and functional safety required by multi-domain automotive applications..



сђљJob DescriptionсђЉ

сЃ╗Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration

сЃ╗Design and implement graphРђЉlevel optimizations (operator fusion, quantizationРђЉaware rewrites, memoryРђЉaware scheduling, partitioning)

сЃ╗Drive performance optimization for target NPUs, including tiling, tensor layout, and multiРђЉcore execution strategies

сЃ╗Partner with SoC and AI accelerator architects to influence hardware features through compiler insights

сЃ╗Own performance KPIs for real automotive AI workloads using simulators, profilers, and siliconРђЉcorrelated models

сЃ╗Ensure compiler outputs meet automotive requirements (realРђЉtime behavior, determinism, quality expectations)

сЃ╗Mentor senior engineers and set technical direction without peopleРђЉmanagement responsibilities



сђљImpact & DifferentiatorsсђЉ

RenesasРђЎ Gen5 R-Car automotive SoC lineup, including flagship 3 nm devices like the R-Car X5H, is among the first highly integrated multi-domain automotive SoCs built on advanced 3 nm process technology, designed to run ADAS, IVI, gateway, and next-gen SDV workloads on a centralized platform. These platforms deliver high AI performance (e.g., multi-hundreds of TOPS), scalable chiplet-based acceleration, and power efficiency tailored for electrified and autonomous vehicles while meeting stringent functional safety standards. An AI Compiler Engineer enables this hardware vision by ensuring that state-of-the-art AI models and computational kernels are efficiently mapped to the silicon fabric Рђћ directly enhancing performance, reducing latency and energy, and accelerating software adoption in automotive ecosystems where compute efficiency and safety are paramount.

сђљMust-HaveсђЉ

сЃ╗MS/PhD (or equivalent experience) in Computer Science, EE, or related field

сЃ╗Deep experience building AI compilers, accelerator backends, or graph optimization frameworks

сЃ╗Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators

сЃ╗Experience with MLIR, LLVM, TVMРђЉlike systems, or proprietary compiler IRs

сЃ╗Excellent C/C++ and Python skills

сЃ╗Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)

сЃ╗Strong communication skills are required, e.g. agile development experience in Scrum team (Scrum Master or member)



сђљNice-to-HaveсђЉ

сЃ╗Experience with automotive or safetyРђЉcritical systems

сЃ╗Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)

сЃ╗Performance modeling or hardwareРђЊsoftware coРђЉdesign experience

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