Senior ASIC/SoC Validation Engineer – PCIe & FPGA Prototyping

We are seeking an experienced ASIC/SoC Validation Engineer with strong hands-on expertise in FPGA prototyping and emulation platforms. In this role, you will be responsible for enabling and validating PCIe, LPDDR, and ONFI subsystems on pre-silicon platforms such as ZEBU and HAPS. You will collaborate with cross-functional global teams to drive SoC bring-up, debug complex hardware and RTL issues, and ensure stable system-level validation. Success in this position requires strong technical ownership, effective problem-solving skills, and the ability to deliver robust pre-silicon validation solutions that accelerate product development.

• Deploy and validate SoC designs on pre-silicon emulation and prototyping platforms such as ZEBU and HAPS.
• Perform PCIe bring-up, validation, and debugging across FPGA and emulation environments.
• Support LPDDR and ONFI subsystem implementation and validation activities.
• Work with Xilinx FPGA devices using Vivado and Synopsys ProtoCompiler tool flows.
• Debug hardware, FPGA, and RTL issues to identify root causes and drive resolutions.
• Modify and debug Verilog RTL as required for validation and issue resolution.
• Collaborate with SoC, firmware, application engineering, and global design teams during bring-up and validation.
• Analyze debug logs, traces, and system behavior to improve platform stability.
• Support interoperability testing and end-to-end validation of pre-silicon systems.
• Contribute to continuous improvements in emulation, prototyping, and validation methodologies.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in ASIC/SoC validation, FPGA prototyping, or pre-silicon validation.
• Hands-on experience with ZEBU and/or HAPS platforms.
• Strong understanding of PCIe architecture and validation methodologies.
• Practical experience with Xilinx UltraScale or newer FPGA devices and Vivado.
• Hands-on knowledge of Synopsys ProtoCompiler flow.
• Experience with FPGA and RTL debugging techniques.
• Proficiency in Verilog RTL debugging and analysis.
• Strong analytical and problem-solving skills.

• Experience with LPDDR, ONFI, or NVMe protocols.
• Knowledge of transactor-based emulation environments.
• Experience with SERDES configuration and high-speed interface debugging.
• Familiarity with SoC integration and system-level validation.
• Ability to work effectively in a collaborative, global engineering environment.
• Strong verbal and written communication skills.