RTL Design Engineer

Position Name – RTL Design Engineer

Type of hiring – Subcon

Location – San Jose, CA (Onsite)

Job Description:

We are hiring an RTL Design Engineer focused on advanced SoC/ASIC design and Flash subsystem development.

Key Responsibilities:

• Design complex digital integrated circuits at block, subsystem, or full-chip level (100M+ gates) using System Verilog
• Develop and define micro-architecture for processor and Flash subsystems
• Work on processor subsystem design involving ARM, RISC-V, or Tensilica cores
• Execute RTL design, synthesis, and timing analysis, collaborating closely with backend/physical design teams
• Contribute across the full SoC/ASIC lifecycle including design, verification, and implementation
• Design and develop programmable Flash controller subsystems
• Partner with design leads/managers to plan and execute development activities
• Support ASIC lab validation, including debugging, issue reproduction, and implementing fixes

Required Skills & Experience:

• Strong hands-on experience with System Verilog-based RTL design
• Solid understanding of SoC architecture and design flows
• Experience in micro-architecture development and documentation
• Proven ability to work on large-scale chip designs (100M+ gates)

Preferred Skills:

• Experience with high-speed interfaces/protocols such as:
• PCIe
• ONFI / Toggle NAND
• DDR4 / DDR5
• NVMe
• Prior experience in Flash memory subsystem design