Lead ASIC DFT Engineer

Job Title : Lead ASIC DFT Engineer

Location : Remote (PST )

Employment Type : Contract (C2C)

JD:

Key skills:

SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC ,PSV, Diagnosys ,Pattern Retargeting, Pattern porting, DRCs, TetraMax, DFTMax

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Required Skills:

• Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Experience with MBIST implementation and verification; SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
• Proven post-silicon debug and silicon bring-up experience.
• Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Strong communication skills and the ability to work independently with minimal ramp-up.