Experience with design on Xilinx products would be a strong plus
expected to communicate effectively with emerging engineers at the India GETC‑I site and provide both technical and process (DO-254) guidance to the verification team.
Core Responsibilities
RTL Design & Simulation: Develop code and testbenches using VHDL, Verilog, and SystemVerilog.
Verification: Create UVM constrained random environments and conduct static timing, linting, and clock-domain-crossing (CDC) analyses.
DO-254 Certification: Create artifacts required for Airborne Electronic Hardware (AEH) DAL-A certification and participate in FAA SOI audits.