Key Skills
PythonPerlVerilogSystemVerilogEDA
Industry
SemiconductorConsumer Electronics
Job Description
Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices!
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use for modifying, analyzing, and verifying RTL. In this role, you will support RTL gatekeeping infrastructure of design and verification collateral as well as soft IP development and release methodologies. Additionally, you will contribute to Perforce administration, ensuring the integrity and performance of our version control ecosystem. You will have the opportunity to maintaining a centralized configuration management system that enables different design views to be loaded into any Front-End flow. An important key aspect of this position is driving innovation through building generative AI solutions across all of these systems and identifying opportunities where AI can accelerate engineering productivity and improve infrastructure reliability. You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at Apple. The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable infrastructure solutions across RTL Design and DV teams within Apple’s HWTech organization. In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups: To create, monitor, and maintain high quality infrastructure and flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple’s chip design efforts.
Minimum of BS degree + 10 years of relevant experience Expertise in programming in Python or Perl Knowledge in Verilog and SystemVerilog
Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing or Lint Understanding of Front-End RTL Build or Construction flows Excellent communication, debug and root causing skills Customer-oriented mindset and support experience Experience in leading large-scale software system development from specification to deployment MSEE/CE/CS preferred
Description
As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification teams use for modifying, analyzing, and verifying RTL. In this role, you will support RTL gatekeeping infrastructure of design and verification collateral as well as soft IP development and release methodologies. Additionally, you will contribute to Perforce administration, ensuring the integrity and performance of our version control ecosystem. You will have the opportunity to maintaining a centralized configuration management system that enables different design views to be loaded into any Front-End flow. An important key aspect of this position is driving innovation through building generative AI solutions across all of these systems and identifying opportunities where AI can accelerate engineering productivity and improve infrastructure reliability. You role will also involve managing internal training materials, keeping them up to date and coordinating vendor trainings so that our Designer/DV engineers are well equipped to do their best job at Apple. The FE RTL Infrastructure - CAD Engineer plays a key role in promoting and driving robust, scalable infrastructure solutions across RTL Design and DV teams within Apple’s HWTech organization. In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the different design groups: To create, monitor, and maintain high quality infrastructure and flows that enable Apple Silicon to produce chips that enable Apple's best products. You will be working with an energized and highly motivated CAD team that comprehensively supports Apple’s chip design efforts.
Minimum Qualifications
Minimum of BS degree + 10 years of relevant experience Expertise in programming in Python or Perl Knowledge in Verilog and SystemVerilog
Preferred Qualifications
Experience with Front-End EDA tools such as Clock Domain Crossing, Reset Domain Crossing or Lint Understanding of Front-End RTL Build or Construction flows Excellent communication, debug and root causing skills Customer-oriented mindset and support experience Experience in leading large-scale software system development from specification to deployment MSEE/CE/CS preferred
Featured Opportunities
Key Skills
PythonPerlVerilogSystemVerilogEDA
Industry
SemiconductorConsumer Electronics