Verification Engineer

We are looking for a skilled and motivated Verification Engineer to join our team!

What you will do

• :Define and implement verification strategies in collaboration with cross-functional teams
• .Develop and maintain a UVM-based environment
• .Write testbenches and verification components using SystemVerilo
• gUse scripting languages (e.g., Python, Perl)

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Requirement

• s:2+ years of experience in ASIC design or verificatio
• n.Strong experience with SystemVerilog and familiarity with UVM methodolog
• y.Effective communication skills and a collaborative mindse

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Location: Tel-A

vivJob Number: 1