DRAM Firmware /Integration Engineer

Omm IT 

📍 Rancho Cordova, United States 🇺🇸

contract
mid-level
on-site
Posted —

Key Skills

DRAMDDR4DDR5PHYECC

Industry

SemiconductorConsumer Electronics

Job Description

Please Note

  •  It is 100% onsite position in Rancho Cordova, CA
  •  Contract role - Need someone to work from office for 5 days in a week.
Key Responsibilities:
  • Develop, validate, and integrate DRAM drivers for the SSD FW platform.
  • Understand DRAM IP on the controller side and develop and validate read, write, gate trainings, and write leveling.
  • Develop expertise in DRAM PHY IP and configure it.
  • Develop expertise in DRAM ECC.
  • Develop expertise in DDR4 and DDR5 protocols.
  • Configure DDR4/DDR5 mode registers and validate those register settings.
  • Develop and validate DDR4/DDR5 initialization.
  • Build and maintain close relationships with internal and external teams.
  • Provide technical expertise to cross-functional teams.
  • Document requirements and track schedules related to each product.


Requirements

​Requirements:

  • Bachelor's or master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
  • Minimum 3 years of experience in the following areas, obtained through schoolwork, classes, research, previous job experience, and/or internship experience.
  • Good understanding of DRAM architecture, operation, and integration.
  • Proficiency with memory testing tools and software.
  • Knowledge of signal integrity, high-speed signal fundamentals, and simulation techniques.
  • Hands-on experience with lab tools such as oscilloscopes, power supplies, and soldering equipment.
  • Good analytical skills and ability to understand and communicate complex concepts.
  • Strong planning and documentation skills.
  • Good communication, interpersonal, and problem-solving skills.
  • Ability to work independently and in a team environment.
  • Develop test procedures and tools for DRAM validation and debugging.

Preferred Qualifications:

  • Strong HW or FW project management and leadership skills.
  • Develop and validate DDR power states and refresh policy.
  • Guide debug efforts to resolve DRAM issues.