Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 1 year of experience with microarchitecture and design of high-performance designs.
• Experience working with power, performance, and area trade-offs.
  
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or a related field.
• Knowledge of accelerators (e.g., Machine Learning or GPUs) or similar high performance designs.
• Understanding of computer architecture/memory subsystem architecture.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Edge TPU is Google's dedicated Machine Learning accelerator, built to power, on-device AI experience including models like gemini.

As an ASIC Design Engineer, you will work with Machine Learning research and Product teams across Google (e.g., gemini, camera, speech, translate, Text-to-Speech (TTS), etc.) to land their on-device machine learning ideas into products with lower latency, better energy efficiency, privacy, offline processing, and lower cost.

In this role, you will deliver the best power/performance/area for ML while enabling new features.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $113,000-$161,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Engage with Machine Learning system architects and Software teams to define specifications.
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
• Provide input on synthesis, timing closure, and physical design of digital blocks.
• Perform power, area and performance trade-offs of digital designs and architectures.
• Apply engineering best practices (e.g. code review, testing, refactoring) to the design and implementation of ASIC blocks.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .