- Take charge of core IP integration in a SoC design, such like MCU/Cache/Busmatrix.
- Take charge of composing slightly complex IPs according to a design spec.
- Help with SoC top clock, reset, power, bus architecture design. Take charge of composing and maintaining SoC top.
- Manage complex FPGA project for FPGA engineers.
- Manage the synthesis environment, exchange data with the BE group for syn. engineers.
- Maintain the simulation environment of a project. Combine the c code compile environment for MCU cores.
- Do IP QA and write c code based test cases for owned IPs, and run RTL/post simulation, analyze results.
- Write sdc for owned IPs. Write and maintain the chip level sdc for both synthesis and STA.
- Write upf and do upf check.
- Write technical documents for all the work above
- Evaluation of hardware elements according to ISO26262 任职要求：
- CS or EE MS/BS 2.6+ years of relevant experiences
- Verilog, C language
- SoC architecture key points 5. low power design skills
- AXI, AHB, APB bus protocol
- TCL for syn
- Perl/Python script
- ISO26262 *公司坚持平等原则，公平公正对待不同背景的员工，包含但不限于国籍、性别、宗教信仰、文化背景等方面，提供平等发展机会，构建多元化人才体系
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