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BTA Design Services Inc.

Staff ASIC Design Engineer - Constraints & RTL

๐Ÿ“ŒKanata, Canada ๐Ÿ‡จ๐Ÿ‡ฆ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Job Description

Weโ€™re hiring! Come and join one of the fastest growing design services companies in Ottawa. Be part of a company that offers interesting work in challenging, stimulating technical environments with companies that lead the world in technology and innovation.

We recognize that our strength is our people, so at BTA Design Services, we foster an environment where everyone on the team is appreciated, trusted and engaged. We also recognize that work / life balance is essential, so we strive to provide our employees with opportunities that challenge and engage them, but allow them to enjoy family, friends and life outside of work.

Key Responsibilities

  • Understand high-level requirements and translate them into detailed specifications.
  • Develop synthesis and timing constraints for complex block and sub-systems
  • Design and implement complex RTL logic (mainly Verilog or System Verilog), run block-level simulation, ASIC synthesis, timing closure.
  • Interface with the verification team, design team, hardware team and support team.
  • Perform lab bring-up, product integration and support.
  • Provide technical support to customers and lead them through complex technical issues

Requirements

The ideal individual is a staff / principal IC Design Engineer with the following...

  • Minimum of an undergraduate degree in EE or equivalent skills/experience.
  • A minimum of 15+ years of relevant experience in progressive roles.
  • Experience with modern day ASIC development including complex RTL logic design, synthesis, STA, lint, LEC, and understanding of PnR.
  • Deep experience developing synthesis and timing constraints for complex logic blocks and sub-systems on large, timing critical digital designs
  • Experience with complex asynchronous clock boundaries & high-speed serial interfaces.
  • Experience in a lab environment, troubleshooting issues up to the system level.
  • Experience or knowledge in one or more of the following required: ARM A** Application Processor Sub-Systems, Processor Fabric Interfaces (ARM preferred, coherent and non-coherent), Caches, Non-Volatile memory, Networking Switch/Router Datapaths, Packet Processing, OTN, Ethernet
  • Experience with industry standard interfaces e.g. 10/25/40/100Gb Ethernet and OTN, PCIe, SPI, I2C, USB, AXI, AHB, AMBA, GPIO, SRIO, DDR/SDRAM/DMA, NV Memories
  • Test verification and scripting experience is a must.
  • Track record as a self-starter, a team player and a leader.

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    ๐Ÿง™โ€โ™‚๏ธ senior

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