Sr Advanced ASIC FPGA Verification Engineer
📌Scottsdale, AZ, United States 🇺🇸
⏱︎ full-time
🧙♂️ senior
💰 148764
hybrid
Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.
Clearance Requirements:
Department of Defense TS/SCI security clearance is preferred at time of hire. Candidates must be able to obtain a TS/SCI clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.
Responsibilities For This Position
Primary Job Qualifications:
We encourage you to apply if you have any of these preferred skills or experiences:
- In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
- In-depth knowledge ofSystem Verilogobject orientedprogramming and theUniversal Verification Methodology (UVM)
- UnderstandsUVM TestbenchArchitectures
- Comfortable using and developing UVMagents, bus functionalmodels
- Understands different types ofcoverage, usage of cover classes, cover points, etc
- Experience with predictive testbench components,functional coverageandassertions
- Experience withconstrained randomtesting
- Experience with theRegister Abstraction Layer
- Familiarity withrequirements-based verification, requirement tracing, and developing requirement verification strategies etc
- Experience with scripting languages such as Linusshell scripts, TCL, Python
- Familiarity with usingFormalVerification tools, code coverage, writing waivers etc
- Familiarity with the following are also helpful
- Questa Verification IP (QVIP)
- Developing UVM testbenches for designs implemented inXilinxdevices with XilinxIPandSoCs
- AXIprotocols, PCIe, Space Wire, and Ethernet interfaces
- DSPfunctions and common signal processing components
- Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
-
Continuous Integration features ofGITLab
- Responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments
- Determines architecture, system simulation and detailed design approach
- Defines module interfaces and all aspects of device design and simulation
- Creates test and simulation plans that establish functional criteria
- Verifies test results and analyzes performance
- May also review vendor capabilities and simulation tools
- Participates in the improvement of the ASIC/FPGA organizational processes
- Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
- May provide leadership and/or direction to lower level employees
- Independently determines approach to solutions
- Contributes to the completion of major programs and projects
-
Plans and executes project tasks for activities described above
- This candidate must have an ability to operate in a team environment and learn new skills to accomplish the verification goals.
- Proficient use and understanding of ASIC/FPGA engineering concepts, principles, and theories
- Proficient in the principles and techniques of ASIC/FPGA design and the design process
- Keeps abreast of technology trends
- Proficient awareness of business objectives and Engineering’s role in achieving
- Proficient in Microsoft Office applications
- Proficient written and verbal communications skills
- Ability to think creatively
- Ability to multi-task
- Proficient skill in communicating issues, impacts, and corrective actions
- Regular contact with senior levels of internal work groups
- Works under limited direction
- Contact with project leaders and other professionals within the Engineering department and with project teams across the company
-
Some contact with external customers
This position is fully on-site or hybrid/flex, as mutually agreed.
While on-site, you will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale
Key Words : Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing
#CJ1
Target salary range: USD $148,764.00/Yr. - USD $165,035.00/Yr. This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
Company Overview
General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!
Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans
Senior Embedded Software Engineer
@ Embedd 
What we're looking for
At embedd.it, we power hardware-software integration in embedded devices. We turn fragmented semiconductor chip data into configurable digital twins, then deterministically generate code, tests, and documentation – making integration faster, cheaper, and resilient to supply chain shocks.
We’re looking for a true legend – someone with abstract thinking and deep expertise in low-level software development. You’ll build vendor-agnostic tooling for MCU and peripheral integration to solve hardware-software integration once and for all. We work at the intersection of embedded systems, code generation, compilers, and machine learning. It’s your chance to help redefine how low-level development is done.
Responsibilities
- Drive the architecture of the driver structures and system layout
- Define scalable patterns for cross-architectural integration across bare-metal, Zephyr, Linux, and other environments
- Deconstruct complex SoC device trees and translate hardware descriptions into structured internal models for automated reasoning
- Partner with the ML team to shape data and annotation models for AI-driven data-extraction tooling
Qualifications
- 5+ years of experience in embedded systems development, including bare-metal and RTOS-based systems
- Proficiency in C/C++
- Familiarity with firmware configuration, SoC bring-up, and system-level debugging
- Hands-on experience with code generation tools, or low-level compiler/decompiler/emulator technologies
- Strong background in embedded toolchains: compilers, linkers, debuggers, and build systems
- Python or scripting for automation and tooling is a plus
- Experience with functional-safety standards is a plus
Why embedd.it?
- Dynamic, venture-backed team of engineers challenging the status quo 🚀
- Work at the intersection of embedded systems, code generators, compilers, and ML 🤖
- Unusual challenges requiring out-of-the-box abstract thinking 🧠
- Competitive compensation: cash + equity 💰
- Remote work possible 🌍
About Us
embedd.it is a UK-based startup reinventing embedded development. Our platform transforms unstructured semiconductor data into structured digital twins, enabling automatic generation of drivers, tests, and documentation. We're building a single, traceable source of truth to make integration fast, vendor-agnostic, and future-proof.
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Employment
⏱︎ full-time
-
Experience
🧙♂️ senior
-
Salary
💰 148764
-
Working model
hybrid
-
Skills
-
Industry
-
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