SoC Physical Design Engineer, Implementation
📌California, United States 🇺🇸
⏱︎ full-time
🧙♂️ mid-level
💰 132000
SoC Physical Design Engineer, Implementation
Join to apply for the
SoC Physical Design Engineer, Implementation
role at
Google . Responsibilities
Define and implement innovative methodology schemes to improve Performance, Area, and Power. Develop all aspects of ASIC RTL2GDS implementation for designs. Manage physical implementation for partitions. Work with cross-functional teams to deliver results. Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in Physical Design. Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC). Experience in high performance synthesis, PnR, sign-off convergence, including STA and sign-off. Preferred qualifications
Experience with ASIC design flows and methodology of Physical design. Experience in low power design implementation including UPF/CPF, multi-voltage domains, power gating. Experience with scripting languages such as TCI, or Perl. Knowledge of computer architecture, Verilog or SystemVerilog. Understanding of circuit design, device physics, and deep sub-micron technology. About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Qualifications
Candidates should have a strong background in physical design, scripting, and ASIC development, with a focus on performance and power optimization.
#J-18808-Ljbffr
Nice-to-have skills
- Perl
- Verilog
- SystemVerilog
-
California, United States
-
Hardware
- English
Senior Embedded Software Engineer
@ Embedd 
What we're looking for
At embedd.it, we power hardware-software integration in embedded devices. We turn fragmented semiconductor chip data into configurable digital twins, then deterministically generate code, tests, and documentation – making integration faster, cheaper, and resilient to supply chain shocks.
We’re looking for a true legend – someone with abstract thinking and deep expertise in low-level software development. You’ll build vendor-agnostic tooling for MCU and peripheral integration to solve hardware-software integration once and for all. We work at the intersection of embedded systems, code generation, compilers, and machine learning. It’s your chance to help redefine how low-level development is done.
Responsibilities
- Drive the architecture of the driver structures and system layout
- Define scalable patterns for cross-architectural integration across bare-metal, Zephyr, Linux, and other environments
- Deconstruct complex SoC device trees and translate hardware descriptions into structured internal models for automated reasoning
- Partner with the ML team to shape data and annotation models for AI-driven data-extraction tooling
Qualifications
- 5+ years of experience in embedded systems development, including bare-metal and RTOS-based systems
- Proficiency in C/C++
- Familiarity with firmware configuration, SoC bring-up, and system-level debugging
- Hands-on experience with code generation tools, or low-level compiler/decompiler/emulator technologies
- Strong background in embedded toolchains: compilers, linkers, debuggers, and build systems
- Python or scripting for automation and tooling is a plus
- Experience with functional-safety standards is a plus
Why embedd.it?
- Dynamic, venture-backed team of engineers challenging the status quo 🚀
- Work at the intersection of embedded systems, code generators, compilers, and ML 🤖
- Unusual challenges requiring out-of-the-box abstract thinking 🧠
- Competitive compensation: cash + equity 💰
- Remote work possible 🌍
About Us
embedd.it is a UK-based startup reinventing embedded development. Our platform transforms unstructured semiconductor data into structured digital twins, enabling automatic generation of drivers, tests, and documentation. We're building a single, traceable source of truth to make integration fast, vendor-agnostic, and future-proof.
Other similar jobs
Senior ASIC Timing Engineer
@ NVIDIA, 📍United States 🇺🇸
Senior ASIC Timing Engineer
@ NVIDIA, 📍United States 🇺🇸
CPU Physical Design Principal Engineer
@ Qualcomm, 📍United States 🇺🇸
ASIC Analog Design Engineer - REF79515L
@ Continental, 📍United States 🇺🇸
Staff Engineer, Digital IC Design
@ Marvell Technology, 📍United States 🇺🇸
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC Physical Design Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
-
Employment
⏱︎ full-time
-
Experience
🧙♂️ mid-level
-
Salary
💰 132000
-
Skills
-
Industry
-
Find similar jobs
Senior ASIC Timing Engineer
@ NVIDIA, 📍United States 🇺🇸
Senior ASIC Timing Engineer
@ NVIDIA, 📍United States 🇺🇸
CPU Physical Design Principal Engineer
@ Qualcomm, 📍United States 🇺🇸
ASIC Analog Design Engineer - REF79515L
@ Continental, 📍United States 🇺🇸
Staff Engineer, Digital IC Design
@ Marvell Technology, 📍United States 🇺🇸
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC Design Verification Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC Physical Design Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸
ASIC RTL Engineer, Annapurna Labs
@ Amazon, 📍United States 🇺🇸