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Senior RTL Design Engineer

๐Ÿ“ŒYerevan, Armenia ๐Ÿ‡ฆ๐Ÿ‡ฒ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

hybrid

Please note this posting is to advertise potential job opportunities. This exact role may not be open today, but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

You will be in the Silicon One development organization as a senior DFT verification lead in Armenia. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.

Your Impact

  • Taking part in all aspects of digital design, from micro-architecture to RTL design and qualification.
  • Sub-system/SoC integration and verification.
  • Review/enhancement of RTL codes.
  • Improve flows and methodologies to streamline IP/SoC development and integration.
  • Work closely with the verification team for complex debugs to resolve verification failures.
  • Close interaction with physical design team to reach better physical design QoR.

Minimum Qualifications

  • 7+ years of industry experience in ASIC digital design.
  • Proficient in Verilog/System Verilog coding.
  • Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
  • Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.
  • Ability to write scripts using Python, Tcl, Make.
  • Good communications skills, self-motivated and well-organized.

Preferred Qualifications

  • Familiarity with power optimization techniques , power intent (UPF), power estimation.
  • Familiarity with DFT/MBIST is a plus

# WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connectionโ€”we celebrate our employeesโ€™ diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteerโ€”80 hours each yearโ€”allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Working model

    hybrid

  • Skills
  • Industry
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