Bootstrap

RemoteWorker US

Senior ASIC Synthesis Engineer

๐Ÿ“ŒSanta Clara, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

๐Ÿ’ฐ 168000

remote

Senior ASIC Synthesis Engineer At NVIDIA Summary

The Senior ASIC Synthesis Engineer at NVIDIA is responsible for front-end RTL synthesis, gate-level optimization, and timing closure on advanced CMOS technology designs. This role involves collaboration with physical design, DFT, and verification teams to optimize power, area, and timing across multiple design blocks. The position requires expertise in Verilog RTL, EDA synthesis tools, timing analysis, and digital design principles with a focus on low-power and high-performance designs.

Come be a part of new process technology adoption by joining NVIDIA's Advanced Technology Group! Work as part of the advanced technology team to optimize design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you are problem solver and highly motivated individual searching for a collaborative and exciting role, join us today. We encourage applicants with a history of proven success working in a multicultural and diverse environment.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI โ€” the next era of computing. NVIDIA is a โ€œlearning machineโ€ that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our lifeโ€™s work, to amplify human inventiveness and intelligence.

What You'll Be Doing

  • As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and gate level optimization tasks
  • Collaboration with physical design to address timing, area, congestion tradeoffs
  • Drive timing closure and power/area optimization across multiple design blocks
  • Work with DFT and Verification teams to ensure functional and timing correctness

What We Need To See

  • BS or MS in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 8+ years of experience in front-end ASIC synthesis and integration.
  • Deep understanding of Verilog RTL design and digital design principles.
  • Proven experience with industry-standard EDA tools for synthesis (e.g., Synopsys Design Compiler).
  • Hands-on experience with timing analysis, constraint management, and post-synthesis ECO flows.
  • Solid background in low-power and high-performance design optimization techniques.
  • Familiarity with formal verification tools (e.g., Formality/Conformal LEC) and methodologies.

Ways To Stand Out From The Crowd

  • Knowledge of DFT/Test logic including JTAG, scan, high speed I/O loopback, and memory BIST.
  • Have proficiency in programming (Python, Perl, Tcl).

NVIDIA is widely considered to be one of the technology worldโ€™s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.

The base salary range is 168,000 USD - 310,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

You will also be eligible for equity and benefits . NVIDIA accepts applications on an ongoing basis.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Keywords

ASIC synthesis, RTL design, CMOS technology, digital design, EDA tools, timing closure, power optimization, Verilog, physical design collaboration, DFT, low-power design
Other similar jobs

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

CPU Physical Design Principal Engineer

@ Qualcomm, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC Analog Design Engineer - REF79515L

@ Continental, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

Staff Engineer, Digital IC Design

@ Marvell Technology, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC Physical Design Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Salary

    ๐Ÿ’ฐ 168000

  • Working model

    remote

  • Skills
  • Industry
  • Find similar jobs

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    CPU Physical Design Principal Engineer

    @ Qualcomm, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC Analog Design Engineer - REF79515L

    @ Continental, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    Staff Engineer, Digital IC Design

    @ Marvell Technology, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC Physical Design Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“United States ๐Ÿ‡บ๐Ÿ‡ธ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—