Bootstrap

NVIDIA

Senior ASIC Engineer - PMU

๐Ÿ“ŒShanghai, China ๐Ÿ‡จ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

As chip sizes continue to grow, power efficiency has become paramount across all applications - from data centers to automotive and personal computing. Our PMU IP, developed over the past 13 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior ASIC Engineer who can help architect the next generation PMU for AI datacenter.

What Youโ€™ll Be Doing

  • Collaborate with the production SW team and power arch team to define the architecture/micro-architecture for various power features.
  • Learn how PMU's function impacts the system and support the silicon debug.
  • Implement the micro-architecture to RTL design.

What We Need To See

  • BS / MS in electrical / computer engineering.
  • 5 years working experience, with preference given to those with MS or equivalent experience.
  • Strong communication skills and proficient oral English since this role require frequent communication with external teams mainly in USA and India.
  • Familiar with frontend ASIC design.

Ways To Stand Out From The Crowd

  • Experience on active power/low power design.
  • Play similar role in other system-level control features if not power related.

JR1998938

Other similar jobs

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

CPU Physical Design Principal Engineer

@ Qualcomm, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Analog Design Engineer - REF79515L

@ Continental, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Staff Engineer, Digital IC Design

@ Marvell Technology, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC Physical Design Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Skills
  • Industry
  • Find similar jobs

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    CPU Physical Design Principal Engineer

    @ Qualcomm, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Analog Design Engineer - REF79515L

    @ Continental, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    Staff Engineer, Digital IC Design

    @ Marvell Technology, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC Physical Design Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“China ๐Ÿ‡จ๐Ÿ‡ณ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—