Bootstrap

AMD

RTL Design and Low Power Engineer

๐Ÿ“ŒVancouver, Canada ๐Ÿ‡จ๐Ÿ‡ฆ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worldโ€™s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

The ROLE:

The AMD DACC Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge data accelerator technologies powering data center and machine learning workloads. This team is part of the development for tomorrowโ€™s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from power architecture to requirements to execution.



The Person

As a key contributor to the success of AMDโ€™s IP, you will be part of a leading team to drive and improve AMDโ€™s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.



Key Responsibilities

  • Understand the functional and power requirements of the DACC within various SOCs
  • Specializing inโ€ฏRTL design, low-power methodologies, synthesis, and power optimization.
  • Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues
  • Scope requirements and resources to meet project schedules
  • Provide hands on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals
  • Signoff IP quality for delivery into SOC
  • Effectively communicate with multi-disciplined teams located across the globe
  • Gather, attend and present into technical status meetings on a weekly/bi-weekly basis




Preferred Experience

  • Strong UPF, Verilog, System Verilog, TCL, Python (basics)
  • AXI, AHB, I2C
  • Tools fusion Compiler (FC), VCLP, CLP, Power Artist, Primetime, PTPX, Spyglass
  • Strong knowledge Low Power Design (UPF), LINT, CDC, Synthesis, STA, PAGLS Debug
  • Strong knowledge - DDR Subsystem, Turing AI Subsystem, Power Validation, Timing, Closure, ASIC Design Flow
  • Proven RTL design experience on large ASIC development projects
  • Strong background in Verilog and System Verilog
  • Strong analytical skills and attention to detail
  • Excellent written and communication skills
  • Must be a self-starter and able to independently drive tasks to completion
  • Demonstrates the ability to debug issues and quickly identify viable solutions
  • Team player with proven leadership skills




Academic Experience

  • Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering




LOCATION :โ€ฏMarkham,โ€ฏVancouver

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicantsโ€™ needs under the respective laws throughout all stages of the recruitment and selection process.

Other similar jobs

Senior Engineer - RTL Design

@ Alphawave Semi, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL Power/ Design Engineer

@ AMD, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL Engineer- CPU Load/Store Unit

@ Tenstorrent, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL design, Staff Engineer in Hanoi/ HCMC / Danang

@ Synopsys Inc, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

Sr. RTL Design Engineer, Hardware Compute Group

@ Amazon Lab126, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

Silicon RTL Design Engineer

@ AMD, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL Design Engineer, Core-IP

@ Google, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL Design Engineer

@ Google, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

Sr. RTL Design Engineer, Hardware Compute Group

@ Amazon Lab126, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

RTL design Engineer

@ Qualcomm, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

  • Skills
  • Industry
  • Find similar jobs

    Senior Engineer - RTL Design

    @ Alphawave Semi, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL Power/ Design Engineer

    @ AMD, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL Engineer- CPU Load/Store Unit

    @ Tenstorrent, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL design, Staff Engineer in Hanoi/ HCMC / Danang

    @ Synopsys Inc, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    Sr. RTL Design Engineer, Hardware Compute Group

    @ Amazon Lab126, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    Silicon RTL Design Engineer

    @ AMD, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL Design Engineer, Core-IP

    @ Google, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL Design Engineer

    @ Google, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    Sr. RTL Design Engineer, Hardware Compute Group

    @ Amazon Lab126, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

    RTL design Engineer

    @ Qualcomm, ๐Ÿ“Canada ๐Ÿ‡จ๐Ÿ‡ฆ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—