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Altera

RTL Design Engineer

๐Ÿ“ŒSan Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

Job Details

Job Description:

Altera is a global leader in programmable logic and semiconductor solutions. We design cutting-edge technologies that enable innovation across AI, networking, data centers, and embedded applications. Our team is passionate about pushing the boundaries of whatโ€™s possible in silicon design.

Position Overview

We are seeking a highly motivated RTL Design Engineer to join our semiconductor design team. In this role, you will be responsible for designing, implementing, and verifying Register Transfer Level (RTL) code for next-generation semiconductor products. You will collaborate with architects, verification engineers, and physical design teams to deliver high-quality, high-performance designs.

Key Responsibilities

  • Design and develop RTL code for complex digital blocks and subsystems.
  • Collaborate with architects to translate high-level specifications into efficient RTL implementations.
  • Optimize designs for area, power, and performance.
  • Work closely with verification engineers to ensure functional correctness through simulation, emulation, and formal verification.
  • Support integration and debug activities at subsystem and SoC levels.
  • Participate in timing analysis, synthesis, and design-for-test (DFT) reviews.
  • Document design specifications and provide support for cross-functional teams.

Qualifications

Minimum Requirements:

  • Bachelorโ€™s or Masterโ€™s degree in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in RTL design for ASIC/FPGA development.
  • Proficiency in Verilog, SystemVerilog, and/or VHDL.
  • Strong understanding of digital logic design, pipelining, clocking, and reset strategies.
  • Experience with synthesis, static timing analysis, and lint tools.
  • Familiarity with verification methodologies (UVM, SystemVerilog assertions, coverage-driven verification).

Preferred Qualifications

  • Experience with SoC design and integration.
  • Knowledge of low-power design techniques and power-aware flows.
  • Experience with FPGA prototyping and emulation.
  • Familiarity with scripting languages (Python, Perl, TCL, or Shell).
  • Strong problem-solving, analytical, and communication skills.

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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  • Employment

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  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

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