Principal Design Verification Engineer
📌Bengaluru, India 🇮🇳
⏱︎ full-time
🧙♂️ principal
MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs.
Key Responsibilities
- Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure.
- Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
- Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis.
- Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors.
- Employ formal verification techniques to augment random verification and ensure exhaustive coverage.
- Analyze verification coverage metrics to identify and close coverage gaps efficiently.
- Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell.
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Mentor junior verification engineers, providing technical guidance and leadership within the verification team.
- Master`s degree or higher in Electronics, Electrical, Computer Engineering.
- 15+ years of relevant verification experience, specifically in CPU or complex SoC verification.
- Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks.
- Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification.
- Proficiency in SystemVerilog, Verilog, C, C++, and Assembly.
- Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI.
- Strong scripting skills in Python, Perl, TCL, or Shell.
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Experience with CPU architectures, particularly RISC-V, ARM, or MIPS.
- Experience with RISC-V architecture.
- Familiarity with functional safety standards (e.g., ISO 26262).
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Prior exposure to FPGA prototyping and emulation platforms.
- Opportunity to be part of a dynamic team creating industry-leading RISC-V processors.
- Autonomy with extensive support from industry experts.
- Opportunities for significant career growth and technical advancement.
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Competitive compensation and comprehensive benefits package
MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.
Senior Embedded Software Engineer
@ Embedd 
What we're looking for
At embedd.it, we power hardware-software integration in embedded devices. We turn fragmented semiconductor chip data into configurable digital twins, then deterministically generate code, tests, and documentation – making integration faster, cheaper, and resilient to supply chain shocks.
We’re looking for a true legend – someone with abstract thinking and deep expertise in low-level software development. You’ll build vendor-agnostic tooling for MCU and peripheral integration to solve hardware-software integration once and for all. We work at the intersection of embedded systems, code generation, compilers, and machine learning. It’s your chance to help redefine how low-level development is done.
Responsibilities
- Drive the architecture of the driver structures and system layout
- Define scalable patterns for cross-architectural integration across bare-metal, Zephyr, Linux, and other environments
- Deconstruct complex SoC device trees and translate hardware descriptions into structured internal models for automated reasoning
- Partner with the ML team to shape data and annotation models for AI-driven data-extraction tooling
Qualifications
- 5+ years of experience in embedded systems development, including bare-metal and RTOS-based systems
- Proficiency in C/C++
- Familiarity with firmware configuration, SoC bring-up, and system-level debugging
- Hands-on experience with code generation tools, or low-level compiler/decompiler/emulator technologies
- Strong background in embedded toolchains: compilers, linkers, debuggers, and build systems
- Python or scripting for automation and tooling is a plus
- Experience with functional-safety standards is a plus
Why embedd.it?
- Dynamic, venture-backed team of engineers challenging the status quo 🚀
- Work at the intersection of embedded systems, code generators, compilers, and ML 🤖
- Unusual challenges requiring out-of-the-box abstract thinking 🧠
- Competitive compensation: cash + equity 💰
- Remote work possible 🌍
About Us
embedd.it is a UK-based startup reinventing embedded development. Our platform transforms unstructured semiconductor data into structured digital twins, enabling automatic generation of drivers, tests, and documentation. We're building a single, traceable source of truth to make integration fast, vendor-agnostic, and future-proof.
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