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Diligent Tec, Inc

PSV SoC Validation Engineer

๐Ÿ“ŒSan Jose, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

on-site

Job Title: PSV SoC Validation Engineer

Location: San Jose, CA - Onsite






Job Description



We are seeking an experienced PSV SoC Validation Engineer to lead the bring-up, validation, and characterization of advanced SoC platforms. The ideal candidate will possess deep technical expertise in SoC architecture, peripheral validation, and hardware/software integration, with a strong background in post-silicon validation workflows from initial bring-up to production release.





Key Responsibilities





Lead the development and execution of bring-up and silicon validation test plans for SoC platforms.


Validate SoC peripherals, including LPDDRx, PCIe, I2C, and qSPI.


Oversee all phases of the SoC validation lifecycle, from initial bring-up through production release.


Collaborate with cross-functional hardware and software teams to design and execute robust validation and characterization strategies.


Develop and integrate software-based test applications for stress testing and SLT (System Level Test) screening.


Evaluate system performance and hardware/software interactions under diverse operating conditions.


Drive continuous improvement initiatives to enhance validation efficiency, automation, and overall product quality.








Required Skills & Qualifications





Education: B.E/M.E in Electronics & Communication Engineering or related field.


Experience:




10-14 years of SoC validation experience.


Strong background in digital design, circuit design and analysis, computer architecture, and SoC architecture.




Technical Expertise:




Hands-on experience in silicon bring-up, debugging, and characterization of SoC-level IPs (PCIe Gen4/5, LPDDR4/5, PLL/DLL, NOR Flash, SPI, I2C, RISC-V processors).


Proficiency in memory and I/O interface validation.


Knowledge of DDR training and memory system operation (preferred).


Strong programming/scripting skills in C/C++, Perl, Ruby, and Python for automation and GUI development.


Experience with Lauterbach Debugger for RISC-V.


Proficiency in lab equipment usage (oscilloscopes, BERTs, power supplies, logic analyzers).




Additional Knowledge:




Solid understanding of digital design, microarchitecture, timing, power, noise, control systems, firmware, and hardware/software interaction.


Knowledge of signal integrity (SI) and power integrity (PI) is a plus.
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Working model

    on-site

  • Skills
  • Industry
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