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FPGA Design Verification Engineer

๐Ÿ“ŒBengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Role Description

UST Job Title: Technical Lead II - VLSI

Who We Are

At UST, we help the worldโ€™s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impactโ€”touching billions of lives in the process. Visit us at .

The Opportunity

We are seeking a highly motivated and skilled FPGA Verification Engineer to join our dynamic team. In this role, you will be responsible for the verification of complex FPGA designs, ensuring their functionality, performance, and reliability. You will work closely with design engineers to develop and execute verification plans, identify and debug issues, and contribute to the overall quality of our products.

Key Responsibilities

  • Develop and execute comprehensive verification plans for FPGA designs.
  • Create and maintain test benches using industry-standard verification methodologies (e.g., UVM, System Verilog, RTL).
  • Write and debug test cases to verify functionality, performance, and corner cases.
  • Perform code coverage and functional coverage analysis.
  • Identify and debug issues, working closely with design engineers to resolve them.
  • Document verification results and provide clear and concise reports.
  • Participate in design reviews and contribute to the overall verification strategy.
  • Stay up-to-date with the latest verification methodologies and tools.

Required Skills

  • Strong understanding of FPGA, ASIC, RTL design principles and architectures.
  • Proficiency in System Verilog and UVM verification methodology.
  • Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS, Haps).
  • Experience with high-speed I/O design and protocols. Knowledge of PCIe, I2C, SPI, etc.
  • Hands on experience in all aspects of front-end chip development process (e.g., DDR, CDC/RDC, LINT, LEC, etc.).
  • Knowledge of low-power design techniques and power optimization strategies.
  • Knowledge of code coverage and functional coverage analysis.
  • Excellent debugging and problem-solving skills.
  • Strong communication and collaboration skills.

Desired Skills

  • Experience in hardware validation or embedded test automation
  • Hands on with Linux & UNIX operating system.
  • Knowledge of USB, display, power, or input device validation is a plus
  • Exposure to scripting for firmware flashing or device provisioning

Qualification

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in FPGA verification.
  • Experience with scripting languages (e.g., Python, Perl).
  • ASIC design, including RTL design and verification. Hands-on experience with ASIC design
  • Familiarity with hardware description languages (e.g., VHDL, Verilog).

What We Believe

Humility:

We listen, learn, and help selflessly in our interactions

Humanity

We use business to improve lives

Integrity

We honor commitments and act responsibly in relationships

Equal Employment Opportunity Statement

UST is an Equal Opportunity Employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.

Skills

FPGA,RTL,UVM,systemverilog
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