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IBM

EDA Methodology Engineer โ€“ ASIC Formality

๐Ÿ“ŒBengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

Introduction

We are looking for a passionate and experienced EDA Methodology Engineer to join our ASIC design team, focusing on formal equivalence checking using Synopsys Formality. In this role, youโ€™ll work closely with design teams and EDA vendors to develop and implement robust verification flows that ensure functional correctness across design stages.

Your Role And Responsibilities

  • Develop and maintain formal equivalence checking flows using Synopsys Formality.
  • Collaborate with cross-functional teams to align verification methodology with design goals.
  • Implement and support Formality ECO flows for incremental synthesis.
  • Drive methodology improvements for SoC design verification.
  • Coordinate with internal stakeholders and external vendors to deliver high-quality solutions.

Preferred Education

Master's Degree

Required Technical And Professional Expertise

  • Bachelorโ€™s or Masterโ€™s degree in Computer Science, Electronics Engineering, or VLSI Design.
  • 5โ€“8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Conformal LEC, JasperGold).
  • Strong understanding of RTL design languages: VHDL, Verilog, SystemVerilog.
  • Expertise in Tcl and Python scripting.
  • Deep knowledge of logic synthesis and gate-level netlist verification.
  • Experience in setting up and running equivalence checks between RTL and synthesized netlists.
  • Proven ability to troubleshoot and resolve complex verification issues.
  • Strong communication and collaboration skills.

Preferred Technical And Professional Experience

  • Experience with Formality ECO flows.
  • Familiarity with formal verification methodologies in large-scale SoC projects.
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

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