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Digital IC Design Engineer

๐Ÿ“ŒHsinchu City, Taiwan ๐Ÿ‡น๐Ÿ‡ผ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

ไฝœ็‚บ่ฏ้‚ฆ็š„(็ซนๅŒ—) Digital IC Design Engineer ๏ผŒไฝ ๅฐ‡่ฒ ่ฒฌๆŠŠ้—œ็”ขๅ“็”Ÿ็”ข้€ฑๆœŸ็š„ๆฏไธ€้“้—œๅก๏ผŒ็ขบไฟ็”ขๅ“่‰ฏ็އใ€ๆ€ง่ƒฝๅŠๅ“่ณชใ€‚ๅทฅไฝœๅ…งๅฎนๅŒ…ๅซ๏ผš

ใ€ๅทฅไฝœๅ…งๅฎนใ€‘

  • Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization.
  • Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff.
  • Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability.
  • Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).


ๅทฅไฝœๅœฐ้ปž๏ผš็ซนๅŒ—่พฆๅ…ฌๅฎค(ๆ–ฐ็ซน็ธฃ็ซนๅŒ—ๅธ‚ๆ–‡่ˆˆ่ทฏไบŒๆฎต539่™Ÿ)

่˜ๅƒฑๆ€ง่ณช๏ผšๅ…จ่ท

ใ€ๆขไปถ่ฆๆฑ‚ใ€‘

ๅญธๆญท่ฆๆฑ‚๏ผšๅคงๅญธ

็ง‘็ณป่ฆๆฑ‚๏ผš้›ปๆฉŸ้›ปๅญๅทฅ็จ‹็›ธ้—œ โ”‚ ่ณ‡่จŠๅทฅ็จ‹็›ธ้—œ โ”‚

็›ธ้—œ็ถ“้ฉ—๏ผš5ๅนดไปฅไธŠ

่ชž่จ€่ƒฝๅŠ›๏ผš่‹ฑๆ–‡ ้ซ˜็ดš โ”‚ โ”‚

็ฎก็†่ฒฌไปป๏ผšNo

่ผช็ญ้œ€ๆฑ‚๏ผšNo

ๅ‡บๅทฎ้œ€ๆฑ‚๏ผš3ๅ€‹ๆœˆไปฅไธ‹

ๅค–ๆดพ้œ€ๆฑ‚๏ผšNo

ๅ…ถไป–ๆขไปถ๏ผš

  • Experience with logic synthesis tools.
  • Proficient in simulation tools (e.g., VCS) and verification methodologies.
  • Experience collaborating with physical design teams; understanding of floor planning, place & route, and physical constraints.
  • Experience with advanced process nodes (preferably TSMC 16nm/7nm/5nm or similar)


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