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CPU Design Verification Engineer

๐Ÿ“ŒHsinchu, Taiwan ๐Ÿ‡น๐Ÿ‡ผ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Job Description

  • Study CPU uArch and cook solid Verification Plan.
  • Base on DV Plan define and develop UVM, Constraint-Random, C-Based or Formal Verification Environment.
  • Coaching Junior DV Member to effectively achieve DV Milestone.
  • DV Methodology/Tool Evaluation and Deployment to enhance DV quality and efficiency.
  • DV Task Planning and Coordinating Junior Members.

Requirement

  • 5+ Years CPU design verification experience or 6+ Years ARM/RISC-V based SoC/Subsys Verification Experience.
  • OOP and UVM/Constraint Random Methodology Knowledge is required
  • Familiar with CPU or AMBA SoC Arch. (AMBA Protocol, Interconnect, Cache, MMU, TrustZone etc...)

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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

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