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ASIC Design Verification Engineer

๐Ÿ“ŒCalifornia, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

๐Ÿ’ฐ 141000

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Join a stable team developing silicon products for Ethernet systems in the Cloud, creating devices that accelerate AI/ML workflows! This team develops high throughput Ethernet solutions that deliver exceptional performance with power efficiency. We seek highly skilled Constrained Random Design Verification engineers to verify rapidly evolving designs using industry-proven methodologies with SystemVerilog and UVM. Become part of an expert team of engineers involved in all aspects of Design Verification and potential technical leadership. Required Skills

Self-motivated with a strong commitment to quality Team player with excellent collaboration skills Experience with constrained random verification methodologies and coverage closure Preferably skilled in SystemVerilog and UVM, familiar with OOP Tools and Languages

SystemVerilog (including class, SVA, etc.), UVM, VCS, Incisive, scripting skills (Python, Perl, ...) Experience & Education

Bachelor's Degree and at least 12+ years of related experience. Additional Information

Compensation & Benefits

The annual base salary ranges from $141,000 to $225,000. The position is eligible for a discretionary annual bonus and equity awards, following company policies. Broadcom offers a comprehensive benefits package including medical, dental, vision plans, 401(k) with company matching, Employee Stock Purchase Program, Employee Assistance Program, paid holidays, sick leave, and vacation. The company complies with all applicable laws regarding leaves of absence. Equal Opportunity Employer

Broadcom is committed to diversity and equal opportunity. We consider all qualified applicants regardless of race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability, medical condition, pregnancy, veteran status, or other protected characteristics. Applicants with arrest and conviction records will be considered in accordance with local laws. Additional Notes

If located outside the USA, please provide a home address for future correspondence.

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Nice-to-have skills

  • SystemVerilog
  • VCS
  • Python
  • Perl
  • California, United States

Work experience

  • Embedded

Languages

  • English
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  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Salary

    ๐Ÿ’ฐ 141000

  • Skills
  • Industry
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