该职位来源于猎聘 Job Description Contribute to micro-architecture designs for state-of-the-art high-speed low-power digital IPs. Implement design modules using hardware description language (HDL). Design schemes for multi-clock domain crossing and synchronization. Drive OVM/UVM design verification and support FPGA engineers for early prototyping. Execute RTL-to-GDS development flow, including synthesis, schematics design, and supervising custom layout. Check timing closure, and analyze the performance/power/area of designed IPs. Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration. Perform post-layout Hspice simulation to characterize the designed circuit. Assist with test program development, chip bring-up, validation, and production maturity. Job Requirement Master’s degree in Electrical Engineering/Computer Science. 6 months experience as an ASIC Design Engineer or Verification Design Engineer. Proficient with Verilog, SystemVerilog, and Python or Perl. Strong knowledge of micro-architecture design, function modeling, RTL coding, and SoC Integration. Good at multi-clock domain designs, timing analysis, and optimization. Experience in SystemVerilog OVM/UVM, synthesis, mixed-signal circuit schematics design, and layout design. Able to proactively take on responsibilities and competent to work in a start-up environment.