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ASIC Design Engineer - Implementation

๐Ÿ“ŒSunnyvale, United States ๐Ÿ‡บ๐Ÿ‡ธ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Join our Client team and help build next-generation System-on-Chip (SoC) and IP solutions for data center applications. We are looking for experienced ASIC Implementation Engineers with strong front-end expertise spanning RTL to netlist, including RTL linting, CDC analysis, synthesis, timing constraint development, and formal verification.

Key Responsibilities
  • Perform logic and physical synthesis using advanced optimization techniques to generate gate-level netlists optimized for timing, area, and power.
  • Identify and resolve timing, area, and congestion issues in collaboration with RTL and physical design teams.
  • Conduct power estimation at RTL and gate level, and drive power reduction initiatives.
  • Execute formal verification checks between RTL and gate-level netlists; debug issues such as aborts, inconclusive results, and logic equivalency failures.
  • Run RTL lint and manage waivers in coordination with design teams.
  • Perform RTL-level DFT (Design for Test) analysis and enhance stuck-at fault coverage.
  • Develop and maintain timing constraints for RTL synthesis and PrimeTime STA across block and SoC top levels, including inter-block timing analysis and IO budgeting.
  • Create automation scripts and contribute to methodology development for front-end tools (Lint, CDC, RDC, Synthesis, STA, Power).
  • Support design, DV, and emulation teams with handoff and integration tasks; provide timing and congestion feedback to physical design teams.
Minimum Qualifications
  • 10+ years of experience in ASIC front-end synthesis and SoC integration.
  • Deep knowledge of RTL synthesis and optimization for power, performance, and area (PPA).
  • Strong understanding of ASIC front-end and back-end flows and tools.
  • Proficient in RTL design using SystemVerilog or similar HDL.
  • Proven track record of managing multiple design releases and resolving cross-functional PPA issues.
  • Excellent communication and collaboration skills with internal teams and EDA vendors.
  • Bachelorโ€™s degree in Computer Science, Electrical/Computer Engineering, or equivalent practical experience.
Preferred Qualifications
  • Experience in SoC integration and front-end implementation for large-scale designs.
  • Familiarity with physical design concepts including floorplanning, CTS, and routing.
  • Strong understanding of timing and physical libraries, including SRAM memories.
  • Hands-on experience with timing signoff methodologies (AOCV, POCV).
  • Knowledge of low-power design techniques and analysis.
  • Proficiency in scripting (Python, Tcl) and automation for EDA tool flows.
  • Experience with tools such as Synopsys Design Compiler, PrimeTime, Formality, and Spyglass.

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